A phase-locked loop (PLL) is an electronic circuit that controls a voltage-controlled oscillator (VCO) frequency for maintaining a constant phase angle/frequency relative to a reference signal. In telecommunications, the oscillator is usually a part of the receiver and/or transmitter. A digital PLL circuit may consist of a serial shift register which receives a digital control which is extracted using the received signal, a stable local clock signal which supplies clock pulses to the shift register to drive it and a phase comparator circuit which uses the local clock and a PLL-induced signal to match the VCO frequency to a received signal. A basic PLL can comprise a reference oscillator, a phase/frequency detector, a loop filter, a VCO and a divider.
FIG. 1 shows an example of a block diagram of a phase-locked loop (PLL) with a voltage-controlled oscillator 200 that provides an output signal 220, according to the prior art. A control block 202 provides digital tuning to the circuit. The output lines 204, 206, 208 of the control block 202 control the digital frequency tuning circuit of the VCO 200. Typically the PLL comprises also a divider block 210 that divides the frequency of the output signal by a predetermined number N (integer or fractional), thus providing a divided output frequency signal 211. A phase detector 214 utilizes a reference frequency signal 212 and a filtering block (e.g. a low pass filter, LPF) 216 in a feedback loop to the VCO 200. The phase detector 214, which includes a charge pump, is used to generate a dc voltage to control VCO 200 output frequency. The dc voltage is proportional to the frequency difference of an output frequency signal 211 and the reference frequency signal 212. Any higher frequency signal in the phase detector 214 output is filtered with a filter 216 to reduce noise in the VCO 200. An example of a conventional tuning method of a voltage-controlled oscillator is described in a patent publication EP 1 220 454.
PLLs are widely used as frequency synthesizers in many applications where it is necessary to generate signals with precise frequency, with low spurs and good phase noise. VCO's frequency in PLL operation may be changed by varying the reference frequency or the divisor. An integer PLL is a well-known circuit with simplicity and robustness. However, the channel spacing in an integer PLL is limited to the multiples of a reference clock. This causes problems in PLL settling time design or, in contrast, causes limited sized channel spacing.
The foregoing problem is usually solved with a fractional division ratio PLL. However, the fractionality brings other problems to the design, for example spurs. One solution to lower the spurs has been a Sigma-Delta modulation type of noise re-shaping. However, PLL circuits with Sigma-Delta modulation are very complicated and space consuming. Further, the known methods concentrate on correcting the flaw effects in a fractional PLL operation rather than removing the flaws themselves.